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Stacked GaAs FET RF Power Amplifiers
John McRory (supervisor: Dr. Ron Johnston)
Ph.D. Thesis, The University of Calgary, December 1997
This dissertation deals with the design, simulation, analysis, and
experimental testing of a new device configuration for GaAs high
frequency power amplifiers called the stacked FET. In this
configuration the output drain to source connections of the FETs are
placed in series forming a stack of outputs extending from Vdd to ground, while the input signal is fed to each device through an
isolation transformer. The stacked FET offers an improved output
impedance, increased system efficiency, and can operate from a much
higher drain to source voltage than a standard design.
Two test MMIC amplifiers have been designed and simulated using the
HP/EESOF Libra harmonic balance simulator, and fabricated using Nortel's
cellular GaAs sagfet process. These MMICs were combined to form three
experimental power amplifiers: a single FET amplifier, a two FET stack,
and a four FET stack. The experimental amplifiers were tested using
linear S parameter measurements, one tone tests at 900 MHZ, and two tone
tests at 899.5 MHz and 900.5 MHz, and the results are compared with the
results from the harmonic balance simulation.
A new large signal analysis is proposed based on the describing
functions used in nonlinear system theory. Describing functions for the
one and two tone tests are developed using the dc transfer
characteristic of the MESFET which is derived while it is connected to
the maximum output power load resistance. The fundamental, harmonic,
and intermodulation powers are predicted and compared with the measured
amplifier results and with the harmonic balance simulation results.
CONTACTS: John McRory, Ron Johnston
SUBJECTS: RF Circuits and Systems
TYPE: Thesis
PUBLISHED: 1997
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