Guidelines for the Noise Optimization of 0.18um CMOS Tuned LNAsAhmed Youssef, Jim Haslett
The 47th IEEE International Midwest Symposium on Circuits and Systems, Hiroshima, Japan, Vol. III, pp. 9-12, July 25-28, 2004
Based on four noise parameters and two-port noise theory, considerations for noise optimization of fully integrated tuned low-noise amplifier (LNA) designs are presented. This paper demonstrates explicit design guidelines for a 0.18 micron CMOS tuned LNA. These guidelines give a useful indication of the design tradeoffs between noise figure, power dissipation and gate overdrive voltage for the LNA designed using this technology.
CONTACTS: Ahmed Youssef, Jim Haslett
SUBJECTS: RF Circuits and Systems
TYPE: Conference Publication
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